{
    "2.1" : {
        "docs" : [
            { "CHANGELOG"    : "$BASEURL/CHANGELOG.TXT" }
        ],
        "components" : {
            "fpga" : [ 
                {
                    "description": "FPGA",
                    "version" : "2.1",
                    "hw_constraint" : { "fpga": { "max": 7 }},
                    "md5" : "a8ae1cb08825adeb1e6187a695dbfa33",
                    "file": "flx_madi_256.rpd", 
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                },
                {
                    "description": "FPGA",
                    "version" : "2.1",
                    "hw_constraint": { "fpga": { "min": 8 }},
                    "md5" : "5e4f77132e748659fbb54e6d90edafb8",
                    "file": "flx_madi_484.rpd", 
                    "method": "fpgaflasher",
                    "connection": "uart-fpgaflash" 
                }
            ]
        }
    }
}